The number of bits available for the ADC architecture is limited by speed and power constraints, and currently, for example, for an ADC sampling at 125 MHz, the resolution is limited to 7 bits. The 100-Mbit Ethernet standard calls for at least 7 bits. To illustrate an example of the impact of this limited ADC resolution upon receive channel performance, a 2V peak-to-peak differential signal at a transmitter attenuates to a pulse response of only 185 mV in amplitude (differential) after travelling 150 meters of the 100-Mbit Ethernet cable. Since the ADC architecture must be able to handle a full signal range, which may extend from about 120 mV to the full 2V peak-to-peak with a long sequence of ones, the ADC architecture must allocate available bits to the full range. For example, a 6-bit ADC has only a few bits to quantize a pulse response as small as 120 mV in the above full signal range.